1. Field of the Invention
This invention relates generally to diagnostics of a Peripheral Component Interconnect (PCI) Bus. More particularly, it relates to a technique for determining statistics relating to the usage of a PCI Bus.
2. Background of Related Art
The Peripheral Component Interconnect (PCI) Bus is fast becoming the bus of choice for personal computers, eventually eliminating the traditional Industry Standard Architecture (ISA) bus. The PCI Bus is a standard for connecting peripherals to a personal computer, released in the Fall of 1993. PCI is supported by most major manufacturers, with initial implementations running at 33 MHz. PCI is processor independent and thus can work with various processor architectures.
Technically, PCI is not a bus but a bridge which forwards traffic between network segments, i.e., between peripheral components and the central processor unit (CPU). The PCI Bus includes buffers to decouple the CPU from relatively slow peripherals and allow them to operate asynchronously.
FIG. 5 shows a conventional PCI Bus with a group of conventional components interconnected thereby.
In particular, a primary PCI Bus 102 passes data between a host central processing unit (CPU) 108, PCI slave only devices 116, 118, PCI master capable devices 114, 120, and/or a bridge to a secondary PCI Bus 124. As is defined by the current implementations of the PCI Bus Specification, up to 256 PCI Buses may be bridged in a hierarchy which is somewhat invisible to the primary PCI Bus 102.
The host CPU 108 may be any processor, e.g., microprocessor, microcontroller, or digital signal processor (DSP). The host CPU 108 communicates with a host PCI bridge 104 over a host bus 110. The host bus is a bus having a protocol which typically is specific to the host CPU 108. The host PCI bridge 104 routes signals to and from the host bus 110 either to memory, e.g., synchronous or non-synchronous dynamic random access memory (SDRAM or DRAM) 106, or to other components in communication with the primary PCI Bus 102. The host PCI bridge 104 routes data to and from the host bus 110 based on the addressing of the data, including memory or I/O mapped addressing.
Possible devices communicating over a PCI Bus include PCI bridges 104, 122, master capable devices 114, 120, and slave only devices 116, 118. PCI bridges 104, 122 provide routing of addressed information between different buses. PCI master capable devices are those devices which are capable of initiating and transferring data to any other PCI device on the PCI bus 102, e.g., another processor such as a DSP, or an ASIC with direct memory access (DMA) channels, without any involvement of the host processor. PCI slave only devices 116, 118 are those devices which cannot act as a master or otherwise cannot initiate a data transfer on their own. For example, memory devices.
Each PCI bridge, e.g., the host PCI bridge 104 and the PCI-to-PCI bridge 122 includes logic to implement a PCI bus arbiter 104a, 122a for arbitrating use of the underlying PCI Bus. For instance, the host PCI bridge 104 provides arbitration for the primary PCI Bus 102 between a plurality of request signals REQ by outputting appropriate grant signals GNT to allow use of the PCI Bus by one component at a time. Similarly, the PCI-to-PCI bridge 122 provides arbitration for the secondary PCI Bus 124. Master capable devices arbitrate for use of the primary PCI Bus 102 by activating (i.e., pulling low) the associated request signal REQ, and are given in return a `you're next` signal by an activation of the associated grant signal GNT at the appropriate time based on a predefined arbitration scheme.
Due to the enormous bandwidth available, flexibility, scaleability and interoperability of the PCI Bus, more and more hardware logic is being pushed onto the PCI Bus, e.g., graphic cards for accelerated graphical user interface (GUI) performance, full motion video, audio cards and alternative buses such as the Small Computer System Interface (SCSI) bus. However, the overall system performance of the overall system may be degraded as these high bandwidth functions are pushed onto the PCI Bus due to increased latency in acquiring the PCI Bus and in increased latency or data transfer time for any one data transfer, without regard for individual PCI Bus agent bandwidth requirements.
Conventionally, to determine statistics relating to a PCI Bus such as that shown in FIG. 5, system designers hook up a logic analyzer 500 to the PCI Bus (e.g., primary PCI Bus 102) to manually analyze data patterns transferring across the PCI Bus 102. This technique is time consuming, typically performed when the system is off-line, and/or may not provide statistics for a large number of data transfers on an ongoing basis.
There is thus a need for an efficient and simple PCI Bus diagnostic technique for enabling a user to carefully integrate PCI functions in a host system, and for enabling a user without special training to perform diagnostics on a fully functional PCI Bus.